Compact parallel (m,n) counters based on self-timed threshold logic

Abstract

A new, highly compact implementation of general parallel counters (i.e. population counters) with logic depth 2, based on self-timed threshold logic, is presented. The novel feature of the design is the sharing among all threshold gates of a single capacitive network for computing the weighted sum of all input bits. The significance of the result is the reduction by almost 50% in the required number of capacitors. Interconnect routing cost is also reduced, resulting in significantly decreased total area