Defect tolerant prefix adder design

Abstract

This paper introduces a defect tolerant 64-bit Sklansky prefix adder, designed with the goal of increasing its reliability and extending its lifetime in the presence of hard faults. We consider defect tolerance for early transistor wear-out by exploring the design of fine-grained reconfigurable logic. The approach involves enabling spare processing elements to replace defective elements. Power gating techniques are used to disable faulty logic blocks and enable spare logic. Minimum sized transistors are used for spare processing elements to reduce area overhead, and simplify reconfiguration interconnect. The performance of the design is compared to a baseline, non-repairing design using the cost metrics of: area overhead, power consumption, and performance in the fault free and faulty case